Real‐time, high resolution wafer mapping of critical medium current ion implants can reveal “device killing” problems well before parametric binning at electrical test. Device fails associated with electrical testing at the “End Of Line” have been correlated to mechanical scan problems that can be monitored with a spatially significant Dynamic Surface Charge, wafer metrology technique. High‐resolution mapping allows implant “Micro‐Uniformity” to be evaluated in real time, enabling metrology of device‐critical implant parameters before “End Of Line” electrical testing.
